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| 型號(hào)： | HCD404344R |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-series microcomputer(4位單片微計(jì)算機(jī)) |
| 中文描述： | 4位HMCS400系列微電腦（4位單片微計(jì)算機(jī)） |
| 文件頁(yè)數(shù)： | 12/212頁(yè) |
| 文件大?。?/td> | 700K |
| 代理商： | HCD404344R |
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Rev. 1.0, 03/99, page 9 of 209
b. Timer B is an 8-bit multifunction timer (free running/event counter/reload timer/input
capture
timer B functions.
*1
). In this example task, timer B is used as a reload timer. Table 1 describes the
Table 1
Timer B Functions
Timer Mode Register B1 (TMB1)
Function
TMB1 is a 4-bit write-only register. It selects the timer B function (free-running/reload
timer) and operating clock. TMB1 is initialized to $0 when reset and in stop mode.
Timer Write Register BL, U (TWBL, TWBU)
Function
TWBL and TWBU form an 8-bit write-only register, which is made up of the lower digit
(TWBL) and upper digit (TWBU). TWBL and TWBU are used for the initial TCB
setting (the reload setting when operation as a reload timer).
Timer Counter B (TCB)
Function
TCB is an 8-bit up-counter, which is incremented by the input internal clock. The TCB
input clock is selected using bits TMB12 to TMB10 of TMB1. The value written to
TWBL and TWBU is also written to TCB. When TCB overflows, the timer B interrupt
request flag (IFTB) is set to “1”. If, at this point, timer B is set as a reload timer, the
value of TWBL and TWBU is written to this counter and the count starts from this
value. TCB is initialized to $00 when reset and in stop mode.
Prescaler S (PSS)
Function
PSS is an 11-bit counter to which the system clock is input when in active mode and
standby mode, and the subsystem clock is input when in subactive mode
initialized to $000 at a reset, and division of the system clock starts when the reset is
canceled. PSS operation is halted when reset, in stop mode, and in watch mode
However, it runs in other operating modes. The PSS output is shared by the internal
peripheral modules, the division ratio being set independently for each of the internal
peripheral modules.
2
PSS is
2
.
Timer B Interrupt Request Flag (IFTB)
Function
IFTB reflects the existence of the timer B interrupt request. When timer B overflows,
IFTB is set to “1”. IFTB can only be read/written to (only “0” can be written) using bit
operation commands. Note that IFTB is not automatically cleared even when the
interrupt is received, and must be cleared by writing “0” using software. IFTB is
cleared at a reset and in stop mode.
Timer B Interrupt Mask (IMTB)
Function
IMTB is the bit that masks IFTB. When IFTB is set to “1” and, additionally, IMTB is
“0”, a timer B interrupt request is sent to the CPU (when IE = “1”). If IFTB is set to “1”
but IMTB is “1”, no interrupt request is sent to the CPU and the timer B interrupt is
held. IMTB can only be read or written to using bit operation commands. It is set to
“1” at a reset and in stop mode.
Notes: 1. Applies to H4318/H4359/H4369 Series only. In the H4344/H4889 Series, timer B has
no input capture function.
2. Applies only to H4369/H4889 Series.
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