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    參數(shù)資料
    型號(hào): HCC4536B
    廠商: 意法半導(dǎo)體
    英文描述: Dual J-K Flip-Flops With Preset And Clear 16-CFP -55 to 125
    中文描述: 可編程定時(shí)器
    文件頁(yè)數(shù): 12/17頁(yè)
    文件大?。?/td> 351K
    代理商: HCC4536B
    Functional Test Sequence
    Outputs
    Decade Out
    Q1 Thru Q24
    0
    0
    Inputs
    Comments
    In1
    Set
    Reset
    8-Bypass
    All 24 steps are in reset mode.
    1
    1
    0
    1
    1
    1
    1
    1
    Counter is in three 8-stage section in parallel
    mode.
    First ”1” to ”0” Transition of Clock
    0
    1
    0
    0
    1
    1
    1
    0
    1
    1
    1
    255 ”1” to ”0” transitions are clocked in the
    counter.
    1
    1
    1
    1
    The 255 ”1” to ”0” Transition
    Counter converted back to 24 stages in series
    mode.
    Set and Reset must be connected together and
    simultaneoulsy go from ”1” to ”0”.
    In
    1
    switches to a ”1”.
    Counter Ripples from an all ”1” state to an all ”0”
    state.
    0
    0
    0
    0
    1
    1
    0
    0
    0
    0
    0
    0
    0
    1
    0
    Input Voltage.
    QuiescentDevice Current.
    TEST CIRCUITS
    FUNCTIONAL TEST SEQUENCE
    TestFunction has beenincluded forthe reduction of
    test time required to exercise all 24 counter stages.
    This test function divides the counter into three 8-
    stage section and 255 counts are loaded in each of
    the 8-stage sectionsin parallel. All flip-flops arenow
    at a ”1”. The counter is now returned to the normal
    24-steps in series configuration. One more pulse is
    enteredintoIn
    1
    whichwillcausethecounter toripple
    from an all ”1” stateto an all ”0” state.
    HCC/HCF4536B
    12/17
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