參數(shù)資料
型號(hào): HCC4047B
廠商: 意法半導(dǎo)體
英文描述: Dual Line Driver 14-SOIC 0 to 70
中文描述: 低POWELOW功率單穩(wěn)態(tài)/非穩(wěn)態(tài)多諧振蕩器
文件頁(yè)數(shù): 9/15頁(yè)
文件大?。?/td> 302K
代理商: HCC4047B
Figure A
: Retrigger-mode Waveforms.
5 - EXTERNALCOUNTER OPTION
Timet
M
canbeextended byanyamountwiththeuse
of external counting circuitry. Advantages include
digitallycontrolled pulseduration,smalltimingcapa-
citors for long time periods, and extremely fast re-
coverytime.
A typical implementation is shown in fig. B. The
pulse duration at the output is
t
ext
= (N – 1) (t
A
) + (t
M
+ t
A
/2)
Where t
ext
= pulse duration of the circuitry, and N is
the number of counts used.
Figure B
: Implementation of External Counter Option.
6 - POWER CONSUMPTION
In the standby mode (Monostable or Astable),
power dissipation will be a function of leakage cur-
rent in the circuit, as shown in the static electrical
characteristics. For dynamic operation, the power
needed to chargethe external timing capacitor C is
given by the following formula :
AstableMode : P = 2CV
2
f. (Output at Pin 13)
P= 4CV
2
f. (OutputatPin 10and 11)
(2.9CV
2
) (Duty Cycle)
T
Monostable Mode : P=
(Output at Pin 10 and 11)
The circuit is designed so that most of the total
power is consumed in the external components. In
practice, the lowerthe valuesof frequency and volt-
ageused,thecloserthe actualpowerdissipationwill
be to thecalculated value.
Becausethe power dissipation does notdepend on
R, adesign for minimum power dissipation wouldbe
a smallvalue of C.The value of R would depend on
the desired period (within the limitations discussed
above).
7 - TIMING-COMPONENTLIMITATIONS
The capacitor used in the circuit should be non-po-
larized and have lowleakage (i.e. theparallel resist-
ance of the capacitor should be an order of
magnitude greater than the external resistor used).
Threeisno upper orlowerlimit foreitherRorCvalue
to maintain oscillation.
However, in consideration of accuracy, C must be
much larger than the inherent stray capacitance in
HCC/HCF4047B
9/15
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