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參數(shù)資料
| 型號(hào)： | HC646 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Bus Transceivers and D Flip-Flops |
| 中文描述： | 八路三態(tài)總線收發(fā)器和D觸發(fā)器 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | HC646 |
September 1993
6
Philips Semiconductors
Product specication
Octal bus transceiver/register; 3-state
74HC/HCT646
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
An,Bn to Bn,An
39
14
11
135
27
23
170
34
29
205
41
35
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
CPAB,CPBA to Bn,An
66
24
19
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
SAB,SBA to Bn,An
55
20
16
190
38
32
240
48
41
285
57
48
ns
2.0
4.5
6.0
Fig.8
tPZH/ tPZL
3-state output enable
time
OE to An,Bn
47
17
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.9
tPHZ/ tPLZ
3-state output disable
time OE to An,Bn
58
21
17
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.9
tPZH/ tPZL
3-state output enable
time DIR to An,Bn
50
18
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.10
tPHZ/ tPLZ
3-state output disable
time DIR to An,Bn
50
18
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.10
tTHL/ tTLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6 and Fig.8
tW
clock pulse width
HIGH or LOW
CPAB or CPBA
80
16
14
25
9
7
100
24
20
120
24
20
ns
2.0
4.5
6.0
Fig.7
tsu
set-up time
An,Bn to CPAB,CPBA
60
12
10
3
1
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
th
hold time
An,Bn to CPAB,CPBA
35
7
6
2
45
9
8
55
11
9
ns
2.0
4.5
6.0
Fig.7
fmax
maximum clock pulse
frequency
6.0
30
35
21
63
75
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.7
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