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參數資料
| 型號： | HC55171 |
| 廠商： | Intersil Corporation |
| 英文描述： | 5 REN Ringing SLIC for ISDN Modem/TA and WLL |
| 中文描述： | 5任振鈴用戶接口的ISDN調制解調器/電訊和WLL |
| 文件頁數： | 14/18頁 |
| 文件大?。?/td> | 153K |
| 代理商： | HC55171 |
75
Loop Detector Interface
The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set-
ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 16.
SLIC Operating State During Ringing
The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector inter-
face). Figure 17 shows the control interface for the dual
detector interface and the single detector interface.
Additional Application Information
Tip-to-Ring Open Circuit Voltage
The tip-to-ring open-circuit voltage, V
OC
, of the HC55171
may be programmed to meet a variety of applications. The
design of the HC5517 defaults the value of V
OC
to:
Using a zener diode clamping circuit, the default open circuit
voltage of the SLIC may be defeated. Some applications that
have to meet Maintenance Termination Unit (MTU) compli-
ance have a few options with the HC55171. One option is to
reduce the ringing battery voltage until MTU compliance is
achieved. Another option is to use a zener clamping circuit
on V
REF
to over ride the default open circuit voltage when
operating from a high battery.
If a clamping network is used it is important that it is disabled
during ringing. The clamping network must be disabled to
allow the SLIC to achieve its full ringing capability. A zener
clamping circuit is provided in Figure 18.
The following equations are used to predict the DC output of
the ring feed amplifier when using the zener clamping net-
work, V
RDC
.
V
Where V
Z
is the zener diode voltage and V
CE
and V
BE
are
the saturation voltages of the pnp transistor. Using Equa-
tions 31 and 32, the tip-to-ring open-circuit voltage can be
calculated for any value of zener diode and battery voltage.
When the base of the pnp transistor is pulled high (+5V), the
transistor is off and the zener clamp is disabled. When the
base of the transistor is pulled low (0V) the transistor is on
and the zener will clamp as long as half the battery voltage is
greater than the zener voltage.
FIGURE 16. APPLICATION CIRCUIT WIRING FOR SINGLE
LOOP DETECTOR INTERFACE
HC55171
V
RING
24
C
TRAP
V
RING
R
TRAP
D
TRAP
RDO 21
RDI 20
NU 23
ADDITIONAL PULL UP RESISTOR
V
CC
FIGURE 17. DETECTOR LOGIC INTERFACES
F1
RINGING
ACTIVE
ACTIVE
F0
V
RING
MODE
(LOGIC HI)
(LOGIC HI)
RTD
SHD
SHD
VALID DET
F1
RINGING
ACTIVE
ACTIVE
F0
V
RING
MODE
(LOGIC HI)
(LOGIC HI)
SHD
SHD
SHD
VALID DET
(SINGLE DETECTOR INTERFACE)
(DUAL DETECTOR INTERFACE)
V
OC
V
BAT
8
–
FIGURE 18. ZENER CLAMP CIRCUIT WITH DISABLE
EN
+5V
47k
2N2907
V
REF
3
C
IL
HC55171
--------------
V
Z
<
V
RDC
2
V
--------------
4
+
=
(EQ. 33)
V
--------------
V
Z
≥
V
RDC
2
V
–
Z
V
CE
V
BE
–
(
)
+
(
)
4
+
=
(EQ. 34)
V
--------------
V
Z
<
V
OC
V
TDC
2
V
--------------
4
–
–
=
(EQ. 35)
V
--------------
V
Z
≥
V
OC
V
TDC
2
V
–
Z
V
CE
V
BE
–
(
)
+
(
)
4
–
–
=
(EQ. 36)
HC55171
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HC55171_03 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5 REN Ringing SLIC for ISDN Modem/TA and WLL |
| HC55171B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HC55171BEVAL-TRAP1 | 制造商:Harris Corporation 功能描述: |
| HC55171BIB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HC55171BIM | 制造商:Rochester Electronics LLC 功能描述: |
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