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參數(shù)資料
| 型號： | HC55130IMZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SLIC UNIVERSAL LP 28-PLCC |
| 標準包裝： | 37 |
| 系列： | UniSLIC14 |
| 功能： | 用戶線路接口概念（SLIC） |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 2.25mA |
| 功率（瓦特）： | 1.5W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 包括： | 電池跟蹤抗削頂失真，回路和接地鍵檢測，振鈴控制 |
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22
FN4659.13
June 1, 2006
Thermal Shutdown
The UniSLIC14’s thermal shutdown protection is invoked if a
fault condition causes the junction temperature of the die to
exceed about 175°C. Once the thermal limit is exceeded,
both detector outputs go low (SHD and GKD_LVM) and one
of two things can happen.
For marginal faults where loop current is flowing during the
time of the over-temperature condition, foldback loop current
limiting reduces the loop current by reducing the tip to ring
voltage. An equilibrium condition will exist that maintains the
junction temperature at about 175°C until the fault condition
is removed.
For short circuit faults (tip or ring to ground, or to a supply,
etc.) that result in an over-temperature condition, the
foldback current limiting will try to maintain an equilibrium at
about 175°C. If the junction temperature keeps rising, the
device will thermally shutdown and disconnect tip and ring
until the junction temperature falls to approximately 150°C.
Supervisory Functions
Switch Hook Detect Threshold
The Switch Hook Detect Threshold is programmed with a
single external resistor (RD). The output of the SHD pin goes
low when an off hook condition is detected.
Ground Key Detect Threshold
The Ground Key Detect Threshold is set internally and is not
user programmable.
Ringing the Phone
The UniSLIC14 family handles all the popular ringing
formats with high or low side ring trip detection. High side
detection is possible because of the high common mode
range on the ring signal detect input pins (DT, DR). To
minimize power drain from the ring generator, when the
phone is not being rung, the sense resistors are typically
2M
. This reduces the current draw from the ring generator
to just a few microamps.
When the subscriber goes off hook during ringing, the
UniSLIC14 family automatically releases the ring relay and
DC feed is applied to the loop. The UniSLIC14 family has
very low power dissipation in the on hook active mode. This
enables the SLIC (during the ring cadence) to be powered
up in the active state, avoiding unnecessary powering up
and down of the SLIC. The control logic is designed to
facilitate easy implementation of the ring cadence, requiring
only one bit change to go from active to ringing and back
again.
DT, DR AND RRLY INPUTS
Ring trip detection will occur when the DR pin goes more
positive than DT by approximately 4V.
The ring relay driver pin, RRLY, has an internal clamp
between it’s output and ground. This eliminates the need to
place an external snubber diode across the ring relay.
Reducing Impulse Noise During Ringing
With an increase in digital data lines being installed next to
analog lines, the threat from impulse noise on analog lines is
increasing. Impulse noise can cause large blocks of high
speed data to be lost, defeating most error correcting
techniques. The UniSLIC14 family has the capability to
reduce impulse noise by closing the ring relay at zero
voltage and opening the ring relay at zero current.
CLOSING THE RING RELAY AT ZERO VOLTAGE
Closing the ring relay at zero voltage is accomplished by
providing a ring sync pulse to the RSYNC_REV pin. The ring
sync pulse is synchronized to go low at the zero voltage
crossing of the ring signal. The resistor R1 in Figure 18 limits
the current into the RSYNC_REV pin. If a particular polarity
reversal time is required, then make R1 equal to the
calculated value in Equation 39. If a specific polarity reversal
time is not desired, R1 equal to 50k
is suggested.
The RSYNC_REV pin is designed to allow the ring sync
pulse to be present at all times. There is no need to gate the
ring sync pulse on and off. The logic control for the
RSYNC_REV pin cannot be an open collector. It must be
high (push-pull logic output stage / pull up resistor to VCC),
low or being clocked by the ring sync pulse. When the
RSYNC_REV pin is high the ring relay pin is disabled. When
the RSYNC_REV pin is low the ring relay pin is activated the
instant the logic code for ringing is applied.
OPENING THE RING RELAY AT ZERO CURRENT
The ring relay is automatically opened at zero current by the
SLIC. The SLIC logic requires zero ringing current in the
loop and either a valid switch hook detect (SHD) or a change
in the operating mode (cadence of the ringing signal) to
release the ring relay.
If the subscriber goes off hook during ringing, the SHD
output will go low. An internal latch will sense SHD is low and
disable the ring relay at zero ringing current. This prevents
the ring signal from being reapplied to the line. To ring the
line again, the SLIC must toggle between logic states. (Note:
The previous state can not be the Reverse Active State. In
the reverse state, the voltage on the CRT_REV_LVM
FIGURE 18. REDUCING IMPULSE NOISE USING THE
RSYNC_REV PIN AND SETTING THE POLARITY
REVERSAL TIME
RSYNC_REV
24
R1
INPUT FOR THE
RING SYNC PULSE
UniSLIC14
50k
5V
0V
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
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