參數(shù)資料
型號(hào)： HC55120CMZ
廠商： Intersil
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 0K
描述： IC SLIC UNIVERSAL LP 28-PLCC
標(biāo)準(zhǔn)包裝： 37
系列： UniSLIC14
功能： 用戶線路接口概念（SLIC）
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 2.25mA
功率（瓦特）： 1.5W
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 管件
包括： 電池跟蹤抗削頂失真，回路和接地鍵檢測(cè)，振鈴控制
23
FN4659.13
June 1, 2006
capacitor will activate an internal latch prohibiting the ringing
of the line.
Figure 19 shows the sequence of events from ringing the
phone to ring trip. The ring relay turns on when both the
ringing code and ring sync pulse are present (A). SHD is
high at this point. When the subscriber goes off hook the
SHD pin goes low and stays low until the ringing control
code is removed (B). This prevents the SHD output from
pulsing after ring trip occurs. At the next zero current
crossing of the ring signal, ring trip occurs and the ring relay
releases the line to allow loop current to flow in the loop (C).
Operation of Line Voltage Measurement
A few of the SLICs in the UniSLIC14 family feature Line
Voltage Measurement (LVM) capability. This feature
provides a pulse on the GKD_LVM output pin that is
proportional to the loop voltage. Knowing the loop voltage
and thus the loop length, other basic cable characteristics
such as attenuation and capacitance can be inferred.
Decisions can be made about gain switching in the CODEC
to overcome line losses and verification of the 2-wire circuit
integrity.
The LVM function can only be activated in the off hook
condition in either the forward or reverse operating states. The
LVM uses the ring signal supplied to the SLIC as a timebase
generator. The loop resistance is determined by monitoring
the pulse width of the output signal on the GKD_LVM pin. The
output signal on the GKD_LVM pin is a square wave for which
the average duration of the low state is proportional to the
average voltage between the tip and ring terminals. The loop
resistance is determined by the tip to ring voltage and the
constant loop current. Reference Figure 20.
Although the logic state changes to the Test Active State
when performing this test, the SLIC is still powered up in the
active state (forward or reverse) and the subscriber is
unaware the measurement is being taken.
Polarity Reversal
Most of the SLICs in the UniSLIC14 family feature full
polarity reversal. Full polarity reversal means that the SLIC
can: transmit, determine the status of the line (on hook and
off hook) and provide “silent” polarity reversal. The value of
RSYNC_REV resistor is limited between 34.8k (10ms) and
73.2k (21ms). Reference Equation 39 to program the polarity
reversal time.
Transhybrid Balance
If a low cost CODEC is chosen that does not have a transmit
op-amp, the UniSLIC14 family of SLICs can solve this
problem without the need for an additional op-amp. The
solution is to use the Programmable Transmit Gain pin (PTG)
as an input for the receive signal (VRX). In theory, when the
PTG pin is connected to a divider network (R1 and R2
Figure 21) and the value of R1 and R2 is much less than the
internal 500k
resistors, two things happen. First the transmit
gain from VRX to VTX is reduced by half. This is the result of
shorting out the bottom 500k
resistor with the much smaller
external resistor. And second, the input signal from VRX is
also decreased by the voltage divider R1 and R2. Transhybrid
balance occurs when these two, equal but opposite in phase,
signals are cancelled at the input to the output buffer. The
calculation of the value of R2, once R1 is selected, is effected
by the line feed resistors. EQ. 40 can be used to calculate the
value of R2. Where : ZL= Line Impedance, ZTR = input
impedance of SLIC including the protection resistor, and
RP = protection resitors (typical 30).
FIGURE 19. RINGING SEQUENCE
OFF
ON
OFF
RELAY DRIVER
RINGING CURRENT
IN LINE
SHD OUTPUT
RINGING CODE
APPLIED
RING SYNC
PULSE
RINGING VOLTAGE
(A)
(B)
(C)
FIGURE 20. OPERATION OF THE LINE VOLTAGE
MEASUREMENT CIRCUIT
TIP
RING
DT
DR
RING
GEN
GKD_LVM
RING
GEN
FREQ
PULSE WIDTH
PROPORTIONAL TO
LOOP LENGTH
PULSE
LOOP LENGTH
WIDTH
UniSLIC14
R
2
R
1
II500K
1.02
--------------------------
Z
L + ZTR
Z
L + 2Z RP
------------------------------
R
1
II500K
1.02
--------------------------
–
=
(EQ. 40)
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HC55121 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power Universal SLIC Family
HC55121IB 制造商:Rochester Electronics LLC 功能描述:LOW POWER,SLIC,POL/REV/METERING,5301B BALANCE - Bulk
HC55121IBZ 功能描述:電信線路管理 IC LW PWR SLIC POL/REV/MTRING 5301B RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
HC55121IM 制造商:Rochester Electronics LLC 功能描述:LOW PWR SLIC,POL REV/METERING,53DB BALANCE - Bulk
HC55121IMZ 功能描述:電信線路管理 IC LW PWR SLIC POLV/MTRING 53DB RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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