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參數(shù)資料
| 型號： | HC373M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:60V; DC Current Gain Min (hfe):100; Collector Current:10A; Package/Case:3-TO-127; Transistor Polarity:NPN |
| 中文描述： | 八路透明D類鎖存器具有三態(tài)輸出 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 310K |
| 代理商： | HC373M |
CD54HC373, CD74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-V to 6-V V
CC
Operation
Wide Operating Temperature Range of
–55
°
C to 125
°
C
Balanced Propagation Delays and
Transition Times
Standard Outputs Drive up to 15 LS-TTL
Loads
Significant Power Reduction Compared to
LS-TTL Logic ICs
description/ordering information
The ’HC373 devices are octal transparent D-type
latches designed for 2-V to 6-V V
CC
operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74HC373E
CD74HC373E
–55
°
C to 125
°
C
SOIC – M
Tube
CD74HC373M
HC373M
Tape and reel
CD74HC373M96
CDIP – F
Tube
CD54HC373F3A
CD54HC373F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CD54HC373 . . . F PACKAGE
CD74HC373 . . . E OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HC374 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| HC377 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE |
| HC-377 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hybrid Assemblies OPTIC RECEIVER MODULES |
| HC38 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM/HIGH VOLTAGE MULTILAYER CERAMIC CAPACITORS |
| HC-3838 | 制造商:KAI SUH SUH ENTERPRISES 功能描述:CABLE TIE BASE 38*38MM |
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