參數(shù)資料
型號: HB28J128RM3
廠商: Renesas Technology Corp.
英文描述: MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte
中文描述: 多媒體32 MByte/64 MByte/128 MByte/256 MByte/512字節(jié)
文件頁數(shù): 48/91頁
文件大?。?/td> 526K
代理商: HB28J128RM3
HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
Rev.0.02, Sep.15.2004, page 48 of 89
Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S: Start bit (= 0)
T: Transmitter bit (Host = 1, Card = 0)
P: One-cycle pull-up (= 1)
E: End bit (= 1)
Z: High impedance state (-> = 1)
D: Data bits
*: Repeater
CRC: Cyclic redundancy check bits (7 bits for command or response, 16 bits for block data)
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up
resistors R
CMD
respectively R
DAT
. Actively driven P-bits are less sensitive to noise superposition. For the
timing of these Renesas MultiMediaCards, the following values are defined:
Timing Values
Value [clock cycles]
Symbol
Min
Max
Description
N
CR
2
64
Number of cycles between command and
response
N
ID
5
5
Number of cycles between card identification
or card operation conditions command and the
corresponding response
N
AC
2
*
1
TAAC + NSAC
*
2
Number of cycles between a command and the
start of a related data block
N
RC
8
Number of cycles between the last response
and a new command
N
CC
8
Number of cycles between two commands, if
no response will be sent after the first
command (e.g. broadcast)
N
WR
2
Number of cycles between a write command
and the start of a related data block
N
ST
2
2
Number of cycles between stop command and
valid read / write data end
Notes: 1. Refer to Chapter
Electrical Characteristics
for more details about the access time.
2. Refer to Chapter
Read, Write and Erase Time-out Conditions
.
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