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參數(shù)資料
| 型號(hào)： | HB288032MM1 |
| 元件分類： | PROM |
| 英文描述： | FLASH 2.7V PROM CARD, XMA7 |
| 封裝： | CARD-7 |
| 文件頁數(shù)： | 43/80頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HB288032MM1 |
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HB288032MM1
48
Stream write
The data transfer starts N
WR clock cycles after the card response to the sequential write command was
received. The bus transaction is identical to that of a write block command (see Figure “Timing of The
Block Write Command”). As the data transfer is not block-oriented, the data stream does not include the
CRC checksum. Consequently the host can not receive any CRC status information from the card. The
data stream is terminated by a stop command. The bus transaction is identical to the write block option
when a data block is interrupted by the stop command (see Figure “Stop Transmission During Data
Transfer From The Host”).
S T
content
CRC E Z Z P
* * *
P
CMD
Host command
S T
content
CRC E
Card response
NCR cycles
S T
content
Host command
D D D D D D D D D D
E Z Z S L
DAT
* * * * * * * * * * * * * * * * * *
E Z Z Z Z Z Z Z Z
Card is programming
Stop Transmission During Data Transfer From The Host
Erase block timing
The host must first tag the sector to erase. The tagged sector(s) are erased in parallel by using the CMD32-
CMD38. The card busy signalling is also used for the indication of the card erase procedure duration. In
this case the end of the card busy signalling also does mean that the erase of all tagged sectors has been
finished. The host can (also) request the card to send the actual card state using the CMD13.
T
content
CRC
CMD
DAT
CMD
DAT
* * * * * * * *
Z Z * * * * * * * * * * * Z Z Z S L L * * * * * * * * * * * * * * * * * * * * L E
LL E
E
S T
Z
* * * * *
L ... pull down to LOW bit
NCR
S T
content
CRC E
Card response
CRC E
content
card is erasing
card busy
Host command
Host active
Card active
Host active
Card active
Timing of Erase Operation
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相關(guān)代理商/技術(shù)參數(shù) |
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| HB288064A5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:FLASH ATA Card |
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