參數資料
型號: HA9P2425-5
廠商: INTERSIL CORP
元件分類: 運動控制電子
英文描述: 3.2レs Sample and Hold Amplifiers
中文描述: SAMPLE AND HOLD AMPLIFIER, 3.2 us ACQUISITION TIME, PDSO14
封裝: SOIC-14
文件頁數: 5/9頁
文件大?。?/td> 128K
代理商: HA9P2425-5
5-5
Application Information
Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be
adjusted using a 100k
trim pot, as shown in Figure 8. The
recommended adjustment procedure is:
Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and- hold
input voltage causes a -0.06% gain error (C
H
= 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain error
at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a
-10V output.
5. Measure the output hold voltage (V
-10NOMINAL
). Adjust
the trim pot for an output hold voltage of
Figure 8 shows a typical unity gain circuit, with Offset Zero-
ing. All of the other normal op amp feedback configurations
may be used with the HA-2420/2425. The input amplifier
may be used as a gated amplifier by utilizing Pin 11 as the
output. This amplifier has excellent drive capabilities along
with exceptionally low switch leakage.
The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.
The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
85
o
C), Teflon, or Parlene types are recommended.
For more applications, consult Intersil Application Note
AN517, or the factory applications group.
0
+10
5
-5
-10
-15
-20
-25
-30
-35
-10
-5
+5
+10
DC INPUT VOLTAGE (V)
HOLD STEP VOLTAGE (mV)
C
H
= 100pF
C
H
= 1000pF
C
H
= 10,000pF
C
H
= 0.1
μ
F
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
----------------------------------------------------------------------------
(
)
-10V
(
)
+
-IN
+IN
OUT
S/H
CONTROL
OUTPUT
R
I
R
F
0.002R
F
INPUT
S/H CONTROL INPUT
NOTE: GAIN
----------
FIGURE 6. INVERTING CONFIGURATION
+IN
-IN
OUT
S/H
CONTROL
OUTPUT
INPUT
S/H CONTROL
INPUT
NOTE: GAIN ~ 1
-------
+
R
F
R
I
0.002R
I
FIGURE 7. NON-INVERTING CONFIGURATION
IN
V-
100k
OFFSET TRIM (
±
25mV RANGE)
OUT
V+
CONTROL
C
H
-
+
-
+
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
-IN
+IN
V-
V+
GND
CONTROL
OUT
HOLD
CAPACITOR
FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)
HA-2420, HA-2425
相關PDF資料
PDF描述
HA-2420 3.2レs Sample and Hold Amplifiers
HA-2425 3.2レs Sample and Hold Amplifiers
HA1-2425-5 3.2レs Sample and Hold Amplifiers
HA3-2425-5 3.2レs Sample and Hold Amplifiers
HA4P2425-5 3.2レs Sample and Hold Amplifiers
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