參數(shù)資料
型號(hào): HA17524FP
廠商: Hitachi,Ltd.
元件分類: FPGA
英文描述: 3000000 SYSTEM GATE 1.5 VOLT FPGA
中文描述: 開關(guān)穩(wěn)壓器控制器
文件頁數(shù): 2/18頁
文件大小: 88K
代理商: HA17524FP
HA17524P/FP
2
Functional Description
Principals of HA17524 Operation
The HA17524 switching regulator circuit, using pulse width modulation (PWM), is constructed as shown
in figure 1.
Timing resistances R
T
and timing capacitance C
T
control the oscillation frequency. C
T
is charged by a
constant current generated by R
T
. Ramp signals (saw-tooth waves) at the C
T
terminal generated by this
oscillator is available for reference input signal to comparator which control the pulse width.
Ref.
Volt.
+5 V
V
REF
16
+5V
INV. Input
NON-INV. Input
+
+
C.L.
+
+5V
V
CC
COMP
GND
SHUT
DOWN
Error Amp.
Current Limiter
+5V
CL(+)
CL(—)
NOR
NOR
C
1
Q
1
Q
2
E
1
C
2
E
2
+5V
Q
Q
+5 V to internal circuitry
OSC Out
Comparator
R
T
C
T
(Ramp)
1k
10k
Flip Flop
Osc.
3
6
7
1
2
8
10
9
5
4
14
13
11
12
15
Figure 1 HA17524 Block Diagram
The reference voltage connects to the non-inverted or inverted input terminal of the error amplifier via
resistance divider (figure 2).
The output voltage from the error amplifier is compared with the ramp signal capacitance C
T
(figure 1).
The comparator can provide a signal with modulated pulse width.
This signal, then, controls output transistors Q
1
and Q
2
, making an open loop to stabilize output voltage.
Outputs form the error amplifier the current limiter, and the shut-down circuit are connected together at the
comparator, so that an input signal from any one of these circuits can break the output stage.
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