Rev. 3.00, 03/04, page x of xl
2.7.9
Processing States...............................................................................................................49
Usage Notes......................................................................................................................51
2.9.1
Note on TAS Instruction Usage...........................................................................51
2.9.2
Note on Bit Manipulation Instructions ................................................................51
2.9.3
EEPMOV Instruction...........................................................................................52
Effective Address Calculation.............................................................................47
2.8
2.9
Section 3 MCU Operating Modes.....................................................................53
3.1
Operating Mode Selection ................................................................................................53
3.2
Register Descriptions........................................................................................................54
3.2.1
Mode Control Register (MDCR).........................................................................54
3.2.2
System Control Register (SYSCR)......................................................................55
3.2.3
Serial Timer Control Register (STCR)................................................................56
3.3
Operating Mode Descriptions...........................................................................................58
3.3.1
Mode 2.................................................................................................................58
3.3.2
Pin Functions in Each Operating Mode...............................................................58
3.4
Address Map.....................................................................................................................60
Section 4 Exception Handling...........................................................................63
4.1
Exception Handling Types and Priority............................................................................63
4.2
Exception Sources and Exception Vector Table...............................................................64
4.3
Reset .................................................................................................................................66
4.3.1
Reset Exception Handling ...................................................................................66
4.3.2
Interrupts after Reset............................................................................................67
4.3.3
On-Chip Peripheral Modules after Reset is Cancelled ........................................67
4.4
Interrupt Exception Handling ...........................................................................................68
4.5
Trap Instruction Exception Handling................................................................................68
4.6
Stack Status after Exception Handling..............................................................................69
4.7
Usage Note........................................................................................................................70
Section 5 Interrupt Controller............................................................................71
5.1
Features.............................................................................................................................71
5.2
Input/Output Pins..............................................................................................................73
5.3
Register Descriptions........................................................................................................74
5.3.1
Interrupt Control Registers A to D (ICRA to ICRD)...........................................74
5.3.2
Address Break Control Register (ABRKCR) ......................................................75
5.3.3
Break Address Registers A to C (BARA to BARC)............................................76
5.3.4
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................77
5.3.5
IRQ Enable Registers (IER16, IER)....................................................................79
5.3.6
IRQ Status Registers (ISR16, ISR)......................................................................80
5.3.7
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up
Event Interrupt Mask Register (WUEMR3)........................................................81
5.4
Interrupt Sources...............................................................................................................82