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參數(shù)資料
| 型號(hào)： | GVT1256DA18T-5 |
| 英文描述： | x18 Fast Synchronous SRAM |
| 中文描述： | x18快速同步SRAM |
| 文件頁(yè)數(shù)： | 6/24頁(yè) |
| 文件大?。?/td> | 293K |
| 代理商： | GVT1256DA18T-5 |
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CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
6
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 18-bit Write
to occur independent of the BWE and WEn lines and must
meet the set-up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock
’
s rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP
6B
92
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device.
2B
97
CE2
input-
Synchronous
Chip enable: This active HIGH input is used to enable the
device.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes de-
vice to be de-selected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
256K X 18 Pin Descriptions
X18 BGA Pins
X18 QFP Pins
Name
Type
Description
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
(internal)
A...A00
A...A01
Second
Address
Third
Address
(internal)
A...A10
Fourth
Address
(internal)
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
Second
Address
(internal)
A...A01
Third
Address
(internal)
A...A10
Fourth
Address
(internal)
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GVT1256DA18T-6 | x18 Fast Synchronous SRAM |
| GVT71128DA36B-4 | x36 Fast Synchronous SRAM |
| GVT71128DA36B-4.4 | x36 Fast Synchronous SRAM |
| GVT71128DA36B-5 | x36 Fast Synchronous SRAM |
| GVT71128DA36B-6 | x36 Fast Synchronous SRAM |
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|---|---|
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