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參數(shù)資料
| 型號(hào)： | GVT1256DA18T-4 |
| 英文描述： | x18 Fast Synchronous SRAM |
| 中文描述： | x18快速同步SRAM |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大?。?/td> | 293K |
| 代理商： | GVT1256DA18T-4 |
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CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
11
Figure 2. TAP Controller Block Diagram
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
x
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TDI
TDI
[11]
TAP DC Electrical Characteristics
(20
°
C < T
j
< 110
°
C; V
CC
= 3.3V
–
0.2V and +0.3V unless otherwise noted)
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
IH
V
Il
IL
I
IL
I
IL
O
Input High (Logic 1) Voltage
[12, 13]
Input Low (Logic 0) Voltage
[12, 13]
2.0
V
CC
+ 0.3
0.8
V
–
0.3
V
μ
A
μ
A
μ
A
Input Leakage Current
0V < V
IN
< V
CC
0V < V
IN
< V
CC
Output disabled,
0V < V
IN
< V
CCQ
I
OLC
= 100
μ
A
I
OHC
= 100
μ
A
I
OLT
= 8.0 mA
I
OHT
= 8.0 mA
–
5.0
5.0
TMS and TDI Input Leakage Current
–
30
30
Output Leakage Current
–
5.0
5.0
V
OLC
V
OHC
V
OLT
V
OHT
Notes:
11. X = 69 for the x36 configuration. X = 50 for the x18 configuration.
12. All Voltage referenced to V
(GND).
13. Overshoot: V
(AC)<V
+
1.5V for t<t
/2, Undershoot: V
(AC)<
–
0.5V for t<t
/2, Power-up: V
<3.6V and V
<3.135V and V
<1.4V for t<200 ms.
During normal operation, V
CCQ
must not exceed V
CC
. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than t
KHKL
(min.).
14. This parameter is sampled.
LVCMOS Output Low Voltage
[12, 14]
LVCMOS Output High Voltage
[12, 14]
LVTTL Output Low Voltage
[12]
LVTTL Output High Voltage
[12]
0.2
V
V
CC
–
0.2
V
0.4
V
2.4
V
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|---|---|
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