參數(shù)資料
型號(hào)： GTLP18T612GX
英文描述： 18-Bit Bus Transceiver
中文描述： 18位總線收發(fā)器
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 618K
代理商： GTLP18T612GX
7
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
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Test Circuits and Timing Waveforms
500
500
GND
6V
Open
S
CL includes probes and jig capacitance.
From Output
Under Test
CL = 50pF
V
25
CL includes probes and jig capacitance.
For B-Port outputs, CL= 30pF is used for
worst case edge rate
From
Output
Under
Test
30pF
1.5V (GTLP)
1.2V (GTL)
V
t
PHL
t
PLH
0V
1.5V
3.0V
INPUT
1.5V
V
OL
1.0V
V
OH
OUTPUT
1.0V
t
w
Vm V
Input
Vm V
3.0V
0V
Test Circuit for A Outputs
Test Circuit for B Outputs
Voltage Waveforms Pulse Duration
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Propagation
Delay Times (A-Port to B-Port)
Voltage Waveforms Setup and Hold Times
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Propagation
Delay Times (B-Port to A-Port)
Voltage Waveforms Enable and Disable
Times (A-Port)
t
PHL
t
PLH
0V
1.0V
1.5V
INPUT
1.0V
V
OL
1.5V
V
OH
OUTPUT
1.5V
All input pulses have the following characteristics: frequency = 10 MHz, tp = 4 = 2ns, ZO
.
The outputs are measured one at a time with one transition per measurement.
t
SU
t
h
Vm V
Vm V
Data
Input
Timing
Input
Vm V
3.0V
0V
3.0V
0V
All input pulses have the following characteristics: frequency = 10 MHz, tr= tf= 2ns,
ZO= 50
.
The outputs are measured one at a time with one transition per measurement.
t
PZL
Output
Control
0V
3.0V
1.5V
1.5V
1.5V
1.5V
t
PLZ
V
OL
3.0V
0V
t
PZH
t
PHZ
Output
Waveform 1
(S at 6V)
Output
Waveform 2
V
OH
V
OH
-0.3V
V
OL
+0.3V
Waveforn 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high when disabled by the output control. All input
. The outputs are measured one at a time
pulses have the following characteristics: frequency = 10 MHz, tr= tf= 2ns, ZO= 50
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GTLP18T612MEA 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
GTLP18T612MEAX 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
GTLP18T612MTD 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
GTLP18T612MTDX 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
GTLP1B151 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path
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