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參數(shù)資料
| 型號(hào)： | GTLP16612MEA |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UNIV BUS TXRX 18BIT 56SSOP |
| 產(chǎn)品變化通告： | Die Material/Mold Compound Change 10/Sept/2008 |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | 74GTLP |
| 邏輯類型： | 通用總線收發(fā)器 |
| 電路數(shù)： | 18 位 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 管件 |
7
www.fairchildsemi.com
GTLP166
12
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
CL includes probes and jig capacitance.
Test Circuit for B Outputs
CL includes probes and jig capacitance.
For B Port outputs, CL = 30 pF is used for
worst case edge rate.
Voltage Waveforms Pulse Duration
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Setup and Hold Times
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay Times
(A Port to B Port)
Voltage Waveforms Propagation Delay Times
(B Port to A Port)
All input pulses have the following characteristics: frequency
= 10 MHz, t
r = tf = 2 ns, ZO = 50. The outputs are measured
one at a time with one transition per measurement.
Voltage Waveforms Enable and Disable Times (A Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics:
frequency
= 10 MHz, t
r = tf = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTLP16612MEAX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTD | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTD_Q | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTDX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16616 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:17-Bit TTL/GTLP Bus Transceiver with Buffered Clock |
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