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參數(shù)資料
| 型號： | GTLP16612AA |
| 英文描述： | 18-Bit Bus Transceiver |
| 中文描述： | 18位總線收發(fā)器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 618K |
| 代理商： | GTLP16612AA |
1
PS8431 09/24/99
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Product Description
Pericom Semiconductors GTLP series of logic circuits are produced
using the Companys advanced 0.5 micron CMOS technology,
achieving industry leading performance.
The GTLP16612A 18-bit universal transceiver provides TTL to GTLP
signal level translation. The device is designed to provide high-
speed interface between cards operating at TTL logic levels and a
back plane operating at GTLP logic levels. High-speed back plane
operation is a direct result of GTLPs reduced output swing (<1V),
reduced input threshold levels, and output edge-rate control which
minimizes signal settling times. Its function is similar to BTL or GTL
but with modified driver output levels and receiver threshold. GTLP
output low voltage is typically less than 0.5V, the output high is 1.5V,
and the receiver threshold is 1.0V.
Features
Bidirectional interface between GTLP and TTL
logic levels
Designed with Edge Rate Control Circuit to
reduce output noise
V
REF
pin provides external supply reference voltage
for receiver threshold
5V tolerant inputs and outputs on A-Port
Increased B-Port Drive, 50mA
Bus-Hold data inputs on A-Port to eliminate the need for
pull-up resistors for unused inputs
Power up/down high impedance
TTL compatible Driver and Control inputs
A-Port Balanced Drive: 32mA/+32mA
Flow-through architecture
Open drain on GTLP to support wired-or connection
Package:
56-pin 240 Mil Wide Plastic TSSOP (A)
Pin Configuration
Logic Block Diagram
CLK
CI
1D
CE
GTLP
OEAB
CEAB
LEAB
LEBA
CEBA
OEBA
A13
CLKAB
CLKBA
1
56
2
28
29
27
54
B1
55
30
V
CLK
CI
1D
CE
V
1 of 18 Channels
1 of 18 Channels
OEAB
LEAB
CEAB
CLKAB
1
2
A1
A2
A3
A4
A6
A5
A7
A9
A8
A10
A12
A11
A13
A15
A14
A17
A18
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
A16
3
GND
4
5
6
7
V
CC
(3.3V)
8
9
10
GND
11
12
13
14
15
16
17
GND
18
19
20
21
V
CC
(3.3V)
22
23
24
56
55
B
1
54
GND
53
52
51
V
CCQ
(5.0V)
50
49
48
47
GND
46
45
44
43
42
41
40
GND
39
38
37
36
V
REF
35
34
33
GND
25
26
27
LEBA
OEBA
28
GND
32
31
CLKBA
30
CEBA
29
56-Pin
A,V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GTLP16612MEAX | 18-Bit Bus Transceiver |
| GTLP16612MTDX | 18-Bit Bus Transceiver |
| GTLP16616MEAX | Bus Transceiver |
| GTLP16616MTDX | Bus Transceiver |
| GTLP16617MEAX | Bus Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTLP16612MEA | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MEAX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTD | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTD_Q | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTDX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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