參數(shù)資料
型號: GTL2012DP
廠商: NXP Semiconductors N.V.
元件分類: 電壓/頻率轉(zhuǎn)換
英文描述: 2-bit LVTTL to GTL transceiver
封裝: GTL2012DP<SOT505-1 (TSSOP)|<<http://www.nxp.com/packages/SOT505-1.html<1<Always Pb-free,;
文件頁數(shù): 1/14頁
文件大小: 90K
代理商: GTL2012DP
1.
General description
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a
GTL
/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs.
2.
Features
I
Operates as a 2-bit GTL
/GTL/GTL+ sampling receiver or as an LVTTL to
GTL
/GTL/GTL+ driver
I
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
I
GTL input and output 3.6 V tolerant
I
V
ref
adjustable from 0.5 V to 0.5V
CC
I
Partial power-down permitted
I
Latch-up protection exceeds 500 mA per JESD78
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
I
Package offered: TSSOP8 (MSOP8) and VSSOP8
3.
Quick reference data
[1]
All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
°
C.
GTL2012
2-bit LVTTL to GTL transceiver
Rev. 01 — 9 August 2007
Product data sheet
Table 1.
Recommended operating conditions; T
amb
= 25
°
C
Symbol
Parameter
C
i
input capacitance
C
io
input/output capacitance
Quick reference data
Conditions
control inputs; V
I
= 3.0 Vor 0 V
A port; V
O
= 3.0 Vor 0 V
B port; V
O
= V
TT
or 0 V
Min
-
-
-
Typ
[1]
2
4.6
3.4
Max
2.5
6
4.3
Unit
pF
pF
pF
GTL; V
ref
= 0.8 V; V
TT
= 1.2 V
t
PLH
LOW-to-HIGH propagation delay
t
PHL
HIGH-to-LOW propagation delay
t
PLH
LOW-to-HIGH propagation delay
t
PHL
HIGH-to-LOW propagation delay
An to Bn; see
Figure 4
An to Bn; see
Figure 4
Bn to An; see
Figure 5
Bn to An; see
Figure 5
-
-
-
-
2.8
3.4
5.2
4.9
5
7
8
7
ns
ns
ns
ns
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