參數(shù)資料
型號(hào): GT-48212
廠商: Galileo Technology Services, LLC
英文描述: Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器)
中文描述: 先進(jìn)的交換式以太網(wǎng)控制器的10 10/100 BaseX(高級(jí)交換式10 10/100 BaseX以太網(wǎng)控制器)
文件頁(yè)數(shù): 1/135頁(yè)
文件大?。?/td> 1619K
代理商: GT-48212
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Galileo
GT-482xx
GT-48212 / GT-48208 / GT-48207
Advanced Switched Ethernet Controllers for 10+10/100 BaseX
Preliminary
Revision 1.2
1/27/99
FEATURES
www.galileoT.com
info@galileoT.com
Tel: 408-367-1400
Fax: 408-367-1401
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Please contact Galileo Technology for possible
updates before finalizing a design.
Single-chip Switched Ethernet Controllers for
10 and 10/100Base-X
- Provides packet switching functions between
eight or 12 Ethernet ports and two Auto-
Negotiated on-chip Fast Ethernet ports
- Switch expansion via Fast MII port
Three versions for different cost/performance
points
- GT-48212: 12 10BaseT ports, two 100BaseX
ports and advanced management features
- GT-48208: eight 10BaseT ports, two 100BaseX
ports and advanced management features
- GT-48207: eight 10BaseT ports, two 100BaseX
ports with no management features
Low-cost 32-bit CPU interface for
management
- Glueless interface to IDT 3041, Motorola
ColdFire, Intel i960R/Jx CPUs, and GT-641xx
controllers.
- Simple interface to other 32/64-bit CPUs
Management CPU not required
- Allows for cost sensitive unmanaged designs
Eight or Twelve 802.3 compliant Ethernet
ports
- 10Mbps Half-Duplex or 20Mbps Full-Duplex
- Serial mode selectable per port: 10Base-T or FL
Two Fast Ethernet Media Access Controllers
- Direct Interface to MII
- Half/Full Duplex Support
- IEEE 802.3 100Base-TX, T4, and FX compatible
- Full MII Management Support (MDC/MDIO)
- Auto-Negotiation supported through MII
Interface
Flow Control on all ports
- Standard 802.3x flow control for Full Duplex
mode
- Back pressure for Half Duplex mode
Direct support for packet buffering
- 1Mbyte: using one device - 256Kx32-bit
Synchronous graphics RAM (SGDRAM)
- 4Mbyte: using two devices - 1Mx16bit SDRAM
- Up to 2K buffers, 1536-bytes each, dynamically
allocated to the receive queues and CPU
High observability LED interface
- Three pin serial LED interface for additional
status information per port
Advanced address recognition on-chip
- Intelligent address recognition mechanism
enables forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Multicast address support in Address Table
- Broadcast storm filtering
Extensive network management support
- Repeater MIB counters allowing implementation
of four RMON groups
- Hardware assist for Spanning Tree algorithm
- CPU access to Address Table
- CPU Query - Ability to read the information from
the Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
Port locking for security
Automatic address aging support
Priority queuing based on MAC address or
802.1Q tag
Port and MAC address based VLAN
IP Multicast support
Flexible software or hardware intervention in
packet routing decisions
Packet sampling management technology
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