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參數(shù)資料
| 型號(hào)： | GSM31P256KB-I66 |
| 英文描述： | x64 Interleaved Burst Mode SRAM Module |
| 中文描述： | X64的交錯(cuò)突發(fā)模式的SRAM模塊 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 51K |
| 代理商： | GSM31P256KB-I66 |
GSI Technology
1/4
09/15/97
256KB / 512KB Modules
GSM31P256KB-I66
GSM31P512KB-I66
COASt 3.1
Specification
GSI TECHNOLOGY
GSM31P256KB-I66
GSM31P512KB-I66
Features
For Intel Pentium CPU based systems
Operates with clock speeds up to 66MHz
Separate 5V and 3.3V power supplies
Low cost and low profile card design using 160 gold
plated leads
Multiple ground pin and decopling capacitors provide
maximum noise protection.
Conform to Intel COASt 3.1 specification
Functional Description
The GSM31P256KB-I66 and the GSM31P512KB-I66 are
the secondary cache module designed for use with Intel Pen-
tium CPU based system. These modules use GSI’s Synchro-
nous Burst SRAMs in plastic surface mount packages
mounted on a multilayer epoxy laminate (FR-4) board.
Pentium is a trademark of Intel Corp.
D[7:0]
WE
A[12:0]
OE
CE CE
A[14:0]
OE
WE[3:0]
D[31:0]
ADSP
ADSC
ADV
CS
GWE
BWE
CE2
CE2
8kx8
5V
32Kx32
Pipelined
Burst
SRAM
Vcc3
A[14:0]
OE
WE[3:0]
D[31:0]
ADSP
ADSC
ADV
CS
GWE
BWE
CE2
CE2
32Kx32
Pipelined
Burst
SRAM
Vcc3
Vcc5
TIO[7:0]
TWE
A[17:5]
ECS2
ECS1
A[17:3]
COE
CWE[3:0]
D[31:0]
ADSP
ADSC
ADV
CCS
GWE
BWE
CWE[7:4]
D[63:32]
CLK0
PD[3:0]
Vcc3,Vcc5
Functional Block Diagram - GSM31P256KB-I66
CLK
NC
GND
Power Supplies
D[7:0]
WE
A[13:0]
OE
CE CE
A[15:0]
OE
WE[3:0]
D[31:0]
ADSP
ADSC
ADV
CS
GWE
BWE
CE2
CE2
16kx8
5V
64Kx32
Pipelined
Burst
SRAM
Vcc3
A[15:0]
OE
WE[3:0]
D[31:0]
ADSP
ADSC
ADV
CS
GWE
BWE
CE2
CE2
64Kx32
Pipelined
Burst
SRAM
Vcc3
Vcc5
TIO[7:0]
TWE
ECS2
ECS1
A[18:3]
COE
CWE[3:0]
D[31:0]
ADSP
ADSC
ADV
CCS
GWE
BWE
CWE[7:4]
D[63:32]
CLK0
PD[3:0]
Vcc3,Vcc5
Functional Block Diagram - GSM31P512KB-I66
CLK
NC
GND
Power Supplies
Functional Description (cont’d)
The GSM31P256KB-I66, and 256KB module, use GSI’s
GS81132Q 32KX32 synchronous burst SRAM and a single
5V 8Kx8 SRAM for the tag. The GSM14P512K-I66, a
512KB module, use GSI’s GS82032Q 64KX32 synchronous
burst SRAM and a single 5V 32Kx8 SRAM for the tag.
The 3.3V data RAM and the 5V tag RAM provide an exact
interface between the module and PC chip set. Four pres-
ence detect bits (PD) allow the system to recognize the type
of cache configuration present.
The low profile card edge package allows 160 signal leads
to be placed on a module, measuring 4.35 inches long, a
maximum of 0.310 inches thick and a maximum of 1.14
inches tall. This compact design allows the OEM to make
better use of the real estate on the mother-board for added
functions or smaller design for cost reduction.
All inputs and outputs and TTL compatible and operate
from two separate 5V and 3.3V power supplies. The use of
multiple ground pins and decoupling capacitors on-board
reduces failure due to noise.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GSM31P512KB-I66 | x64 Interleaved Burst Mode SRAM Module |
| GSM31P256KB-I66 | 256KB Secondary Cache Module Designed For Use With Intel Pen-tium CPU based system(用于英特爾奔騰處理器系統(tǒng)的256KB二級(jí)高速緩沖存儲(chǔ)器) |
| GSM31P512KB-I66 | 512KB Secondary Cache Module Designed For Use With Intel Pen-tium CPU based system(用于英特爾奔騰處理器系統(tǒng)的512KB二級(jí)高速緩沖存儲(chǔ)器) |
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|---|---|
| GSM31P512KB-I66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Interleaved Burst Mode SRAM Module |
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