7
521 - 38 - 02
NOTE:
If an
I
2
C interface is not used, address 0, 1 will force TRS-ID indication on the ancillary data pin. This is to facilitate
applications in which TRS-ID is desired, but an
I
2
C interface is not used. In this case, the SCL clock line must be
connected to the most negative supply.
During the stand-alone mode of operation, flag masking,
video standard override and programmable interrupt features
are disabled. The user can still monitor the video standard and
the error flags through dedicated pins as shown in Table 2.
EDH Passthrough Mode
An EDH passthrough mode is available to aid in system
diagnostics. This mode is selected by address 1,0 on A1, A0
pins. In this mode, the GS9001 will not insert a new EDH
packet into the data stream. Input data is bypassed to output
without modification. Error flag status available through the
I
2
C interface and output pins, is now invalid. However, valid
CRC words can be read through the
I
2
C interface every field,
for a static picture.
The counter can be programmed either to clear automatically
when the counter status is read via the interface, or to clear
when forced through the interface.
I
2
C Serial Communications Interface
The serial communications interface allows access to all error
flags and other internal programmable functions. The Inter-
Integrated Circuit (
I
2
C) protocol is used. For information on
the
GS9001
I
2
C protocol, refer to Document 521 - 59
"
Using
the GS9001 EDH Coprocessor".
The slave addresses for the
I
2
C interface are given in Table 3.
Data formats for the
I
2
C interface READ and WRITE operations
are given in Tables 4 and 5.
I
2
C Address is 00011A
1
A
0
A1
A0
Function
0
0
Available Device Address
0
1
Available Device Address
1
0
EDH Passthrough Mode
1
1
Test Mode
Table 3. I
2
C Slave Addresses