- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄173641 > GS882V37BGB-360I (GSI TECHNOLOGY) 256K X 36 CACHE SRAM, 1.8 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號(hào)： | GS882V37BGB-360I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 36 CACHE SRAM, 1.8 ns, PBGA119 |
| 封裝： | FBGA-119 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 709K |
| 代理商： | GS882V37BGB-360I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
GS882V37BB-360/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
21/26
2003, GSI Technology
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all
logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still
determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then
the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on
the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is
selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a
pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s
output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9012E/E6 | 500 mA, 20 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-226AA |
| GS9012G/E6 | 500 mA, 20 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-226AA |
| GSAA01B-Q03 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 6A, 120VDC, 30.5mm, PANEL MOUNT |
| GSAA03B-Q01 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 6A, 120VDC, 30.5mm, PANEL MOUNT |
| GSAA03B-Q03 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 6A, 120VDC, 30.5mm, PANEL MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS882Z18BD150 | 制造商:G.S.I. 功能描述: |
| GS882Z18CB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。