參數(shù)資料
型號(hào): GS88237CB-200IT
廠商: GSI TECHNOLOGY
元件分類(lèi): SRAM
英文描述: 256K X 36 CACHE SRAM, 2.7 ns, PBGA119
封裝: FPBGA-119
文件頁(yè)數(shù): 22/26頁(yè)
文件大?。?/td> 596K
代理商: GS88237CB-200IT
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
9th Bit Enable
PE
L or NC
Activate DQPx I/Os (x18/x36/x72 mode)
H
Deactivate DQPx I/Os (x16/x32/x64 mode)
GS88237CB-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 7/2009
5/26
2008, GSI Technology
Preliminary
Note:
There are pull-up devices on the ZQ, and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
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