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參數(shù)資料
| 型號： | GS88237BD-200T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 36 CACHE SRAM, 2.7 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 10/29頁 |
| 文件大小： | 859K |
| 代理商： | GS88237BD-200T |
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GS88237BB/D-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 4/2008
18/29
2002, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
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| GS88237CB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.7NS 119FPBGA - Trays |
| GS88237CB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.7NS 119FPBGA - Trays |
| GS88237CB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 2.5NS 119FPBGA - Trays |
| GS88237CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 2.5NS 119FPBGA - Trays |
| GS88237CB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.3NS 119FPBGA - Trays |
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