參數(shù)資料
型號(hào): GS88218BGB-150V
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 512K X 18 CACHE SRAM, 7.5 ns, PBGA119
封裝: ROHS COMPLIANT, FPBGA-119
文件頁(yè)數(shù): 34/35頁(yè)
文件大?。?/td> 1164K
代理商: GS88218BGB-150V
GS88218/36B(B/D)-xxxV
Rev: 1.04 6/2007
8/35
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關(guān)PDF資料
PDF描述
GS88218BGB-200IV 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS88218BGB-200V 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS88218BGB-250IV 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS88218BGB-250V 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS88236BB-150IV 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
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