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參數(shù)資料
| 型號： | GS881E36 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 8Mb（256K x 36Bit)ByteSafe Synchronous Burst SRAM(8M位（256K x 36位）ByteSafe同步靜態(tài)RAM（帶2位脈沖地址計數(shù)器）) |
| 中文描述： | 8MB的（256 × 36Bit）ByteSafe同步突發(fā)靜態(tài)存儲器（800萬位（256K × 36位）ByteSafe同步靜態(tài)隨機(jī)存儲器（帶2位脈沖地址計數(shù)器）） |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 467K |
| 代理商： | GS881E36 |
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Rev: 1.10 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
25/34
2000, Giga Semconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-
compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
1
1
0
0
10 9 8 7 6 5 4 3 2 1
0
x36
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
1
1
x18
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
· · ·
· · ·
n
0
1
2
0
1
2
· · ·
0
1
2
· · ·
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
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| GS881E36AD-133 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
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| GS881E36AD-133T | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
| GS881E36AD-150 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
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