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Rev: 1.04a 3/2009
13/39
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
E1
E2
E3
ADSP ADSC
ADV
W
DQ3
Deselect Cycle, Power Down
None
X
L
X
H
X
L
X
High-Z
Deselect Cycle, Power Down
None
X
L
X
L
X
High-Z
Deselect Cycle, Power Down
None
X
L
X
H
L
X
High-Z
Deselect Cycle, Power Down
None
X
L
X
L
X
High-Z
Deselect Cycle, Power Down
None
X
H
X
L
X
High-Z
Read Cycle, Begin Burst
External
R
L
H
L
X
Q
Read Cycle, Begin Burst
External
R
L
H
L
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
H
L
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
H
F
Q
Write Cycle, Suspend Burst
Current
X
H
T
D
Write Cycle, Suspend Burst
Current
H
X
H
T
D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
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| GS881E32BGD-300I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS881E32BGD-333 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
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