- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299162 > GS88136T-11.5IT (GSI TECHNOLOGY) 256K X 36 CACHE SRAM, 11.5 ns, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | GS88136T-11.5IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 36 CACHE SRAM, 11.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 17/33頁 |
| 文件大小： | 463K |
| 代理商： | GS88136T-11.5IT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
Rev: 1.11 9/2000
24/33
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88118/36T-11/11.5/100/80/66
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-
compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
re
se
n
ce
R
e
g
is
te
r
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
1
10 9 8 7 6 5 4 3 2 1
0
x36
X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1
1
x18
X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
1
2
31 30 29
0
1
2
n
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
相關PDF資料 |
PDF描述 |
|---|---|
| GS881E36BT-150T | 256K X 36 CACHE SRAM, 7.5 ns, PQFP100 |
| GS881E18BD-150 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS881E18BD-150I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS881E18BD-200 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS881E18BD-200I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS88136T-11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| GS88136T-66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| GS88136T-66I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| GS88136T-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| GS88136T-80I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。