參數(shù)資料
型號(hào)： GS88136
廠商： GSI TECHNOLOGY
英文描述： 8Mb（256K x 36Bit)ByteSafe Synchronous Burst SRAM(8M位（256K x 36位）ByteSafe同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）)
中文描述： 8MB的（256 × 36Bit）ByteSafe同步突發(fā)靜態(tài)存儲(chǔ)器（800萬(wàn)位（256K × 36位）ByteSafe同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器））
文件頁(yè)數(shù)： 26/33頁(yè)
文件大?。?/td> 463K
代理商： GS88136
Rev: 1.11 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
26/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe-
less, this RAMs TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis-
ter the RAM responds just as it does in response to the BYPASS instruction described above.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *
Preloads ID Register and places it between TDI and TDO.
1
IDCODE
001
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *
1
SAMPLE/
PRELOAD
100
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
1
BYPASS
111
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
相關(guān)PDF資料
PDF描述
GS88118 8Mb（512K x 18Bit) ByteSafe Synchronous Burst SRAM(8M位（512K x 18位）ByteSafe同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）)
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