參數(shù)資料
型號(hào)： GS8662S36BGD-300
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165
文件頁(yè)數(shù)： 1/37頁(yè)
文件大?。?/td> 748K
代理商： GS8662S36BGD-300
GS8662S08/09/18/36BD-400/350/333/300/250
72Mb SigmaSIOTM DDR -II
Burst of 2 SRAM
400 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.02 3/2011
1/37
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaSIO Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
DLL circuitry for wide output data valid window and future
frequency scaling
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ mode pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaSIO Family Overview
GS8662S08/09/18/36BD are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
JEDEC Std. MO-216, Variation CAB-1
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 4M x 18 has a 2M
addressable index).
Parameter Synopsis
-400
-350
-333
-300
-250
tKHKH
2.5 ns
2.86 ns
3.0 ns
3.3 ns
4.0 ns
tKHQV
0.45 ns
相關(guān)PDF資料
PDF描述
GS88036T-100T 256K X 36 CACHE SRAM, 12 ns, PQFP100
GS88037CT-250I 256K X 36 CACHE SRAM, 2.3 ns, PQFP100
GS880E18GT-66I 512K X 18 CACHE SRAM, 18 ns, PQFP100
GS880F18T-14T 512K X 18 CACHE SRAM, 14 ns, PQFP100
GS880Z18AGT-133I 512K X 18 ZBT SRAM, 8.5 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662S36E-167 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S36E-167I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S36E-200 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S36E-200I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S36E-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM
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