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| 型號(hào)： | GS8644ZV72C-250I |
| 廠(chǎng)商： | GSI TECHNOLOGY |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 1M X 72 ZBT SRAM, 6.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁(yè)數(shù)： | 30/37頁(yè) |
| 文件大?。?/td> | 776K |
| 代理商： | GS8644ZV72C-250I |
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GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
30/37
2003, GSI Technology
JTAG Port Timing Diagram
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input High Voltage
V
IHJ
0.6 * V
DD
V
DD
+0.3
V
1
1.8 V Test Port Input Low Voltage
V
ILJ
–
0.3
0.3 * V
DD
V
1
TMS, TCK and TDI Input Leakage Current
I
INHJ
–
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I
INLJ
–
1
100
uA
3
TDO Output Leakage Current
I
OLJ
–
1
1
uA
4
Test Port Output High Voltage
V
OHJ
1.7
—
V
5, 6
Test Port Output Low Voltage
V
OLJ
—
0.4
V
5, 7
Test Port Output CMOS High
V
OHJC
V
DDQ
– 100 mV
—
V
5, 8
Test Port Output CMOS Low
V
OLJC
—
100 mV
V
5, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Input Under/overshoot voltage must be
–
2 V > Vi < V
DDn
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
V
ILJ
≤
V
IN
≤
V
DDn
0 V
≤
V
IN
≤
V
ILJn
Output Disable, V
OUT
= 0 to V
DDn
The TDO output driver is served by the V
DDQ
supply.
I
OHJ
=
–
4 mA
I
OLJ
= + 4 mA
I
OHJC
= –100 uA
I
OHJC
= +100 uA
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKL
tTKH
tTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
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