參數(shù)資料
型號(hào)： GS8642ZV36E-167IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 2M X 36 ZBT SRAM, 8 ns, PBGA165
封裝： 17 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 24/37頁(yè)
文件大小： 1118K
代理商： GS8642ZV36E-167IT
Product Preview
GS8642ZV18(B/E)/GS8642ZV36(B/E)/GS8642ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
30/37
2004, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input High Voltage
VIHJ
0.6 * VDD
VDD +0.3
V1
1.8 V Test Port Input Low Voltage
VILJ
–0.3
0.3 * VDD
V1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–11
uA
4
Test Port Output High Voltage
VOHJ
1.7
—
V5, 6
Test Port Output Low Voltage
VOLJ
—
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDDQ – 100 mV
—
V5, 8
Test Port Output CMOS Low
VOLJC
—
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V
≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
DQ
VDDQ/2
50
30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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