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參數(shù)資料
| 型號： | GS8642Z36GF-167T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 ZBT SRAM, 8 ns, PBGA165 |
| 封裝： | 1 MM PITCH, LEAD FREE, BGA-165 |
| 文件頁數(shù)： | 20/39頁 |
| 文件大小： | 1021K |
| 代理商： | GS8642Z36GF-167T |
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GS8642Z18(B/F)/GS8642Z36(B/F)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 3/2005
27/39
2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
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PDF描述 |
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| GS8642ZV36E-167IT | 2M X 36 ZBT SRAM, 8 ns, PBGA165 |
| GS8662D11BGD-400 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662D36BD-300IT | 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662DT10BGD-400IT | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8642Z72C-167 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 8NS/3.5NS 209FBGA - Trays |
| GS8642Z72C-167I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 8NS/3.5NS 209FBGA - Trays |
| GS8642Z72C-167IV | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 72MBIT 1MX72 8NS/3.5NS 209BGA - Bulk |
| GS8642Z72C-167V | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 72MBIT 1MX72 8NS/3.5NS 209BGA - Bulk |
| GS8642Z72C-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
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