參數(shù)資料
型號(hào)： GS841Z36CGT-166IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 128K X 36 ZBT SRAM, 7 ns, PQFP100
封裝： ROHS COMPLIANT, TQFP-100
文件頁(yè)數(shù)： 1/28頁(yè)
文件大小： 250K
代理商： GS841Z36CGT-166IT
GS841Z18CGT/GS841Z36CGT
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
250 MHz–100 MHz
3.3 V VDD
2.5 V and 3.3 V VDDQ
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.01 8/2011
1/28
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
256K x 18 and 128K x 36 configurations
User-configurable Pipelined and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleave Burst mode
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
Clock Control, registered, address, data, and control
ZZ Pin for automatic power-down
RoHS-compliant 100-lead TQFP package
Functional Description
The GS841Z18/36CGT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS841Z18/36CGT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS841Z18/36CGT is implemented with GSI's high
performance CMOS technology and is available in a 6/6
RoHS-compliant, JEDEC-Standard 100-pin TQFP package.
Parameter Synopsis
–250
–200
–166
–150
–100
Pipeline
3-1-1-1
tCycle
tKQ
IDD
4.0 ns
2.5 ns
TBD
5.5 ns
3.0 ns
TBD
6.0 ns
3.5 ns
TBD
6.7 ns
3.8 ns
TBD
10 ns
4.5 ns
TBD
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
5.5 ns
TBD
6.5 ns
TBD
7.0 ns
TBD
7.5 ns
TBD
12 ns
TBD
相關(guān)PDF資料
PDF描述
GS842Z18CB-250T 256K X 18 ZBT SRAM, 5.5 ns, PBGA119
GS8641ZV18GE-200 4M X 18 ZBT SRAM, 7.5 ns, PBGA165
GS8644Z18GE-225T 4M X 18 ZBT SRAM, 6.5 ns, PBGA165
GS8662QT10BD-200I 8M X 9 QDR SRAM, 0.45 ns, PBGA165
GS8662QT10BGD-250T 8M X 9 QDR SRAM, 0.45 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS841Z36CGT-200 制造商:GSI Technology 功能描述:100 TQFP - Bulk
GS842Z18AB 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS842Z18AB-100 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS842Z18AB-100I 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS842Z18AB-150 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
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