參數(shù)資料
型號: GS84118T-166
英文描述: x18 Synchronous SRAM
中文描述: x18同步SRAM
文件頁數(shù): 7/30頁
文件大?。?/td> 584K
代理商: GS84118T-166
Rev: 1.05 7/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
7/30
1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Mode Pin Function
LBO
Function
L
Linear Burst
H or NC
Interleaved Burst
FT
Function
L
Flow Through
H or NC
Pipeline
Power Down Control
Note:
There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
ZZ
Function
L or NC
Active
H
Standby, IDD = ISB
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Byte Write Function
Note: H = logic high, L = logic low, NC = no connect
Function
GW
BWE
BW1
BW2
Read
H
H
X
X
Read
H
L
H
H
Write all bytes
L
X
X
X
Write all bytes
H
L
L
L
Write byte 1
H
L
L
H
Write byte 2
H
L
H
L
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