參數資料
型號: GS840
文件頁數: 17/31頁
文件大?。?/td> 717K
代理商: GS840
Rev: 2.05 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
17/31
1999, Giga Semiconductor, Inc.
.
GS84018/32/36T/B-180/166/150/100
AC Test Conditions
Notes:
1.
2.
3.
4.
Include scope and jig capacitance.
Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
Output Load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
.
Device is deselected as defined by the Truth Table.
Parameter
Conditions
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
2.3V
0.2V
1V/ns
1.25V
1.25V
Fig. 1& 2
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
-1uA
1uA
ZZ Input Current
I
INZZ
V
DD
V
IN
V
IH
0V
V
IN
V
IH
V
DD
V
IN
V
IL
0V
V
IN
V
IL
Output Disable,
V
OUT
= 0 to V
DD
I
OH
= - 4mA, V
DDQ
=2.375V
I
OH
= - 4mA, V
DDQ
=3.135V
I
OL
= 4mA
-1uA
-1uA
1uA
300uA
Mode Pin Input Current
I
INM
-300uA
-1uA
1uA
1uA
Output Leakage Current
I
OL
-1uA
1uA
Output High Voltage
V
OH
V
OH
V
OL
1.7V
Output High Voltage
2.4V
Output Low Voltage
0.4V
DQ
VT=1.25V
50
30pF
*
DQ
2.5V
Output Load 1
Output Load 2
225
225
5pF
*
* Distributed Test Jig Capacitance
This Material Copyrighted by Its Respective Manufacturer
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