參數(shù)資料
型號(hào): GS84036T-180T
英文描述: x36 Fast Synchronous SRAM
中文描述: x36快速同步SRAM
文件頁數(shù): 25/31頁
文件大小: 717K
代理商: GS84036T-180T
Rev: 2.05 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
25/31
1999, Giga Semiconductor, Inc.
.
GS84018/32/36T/B-180/166/150/100
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~
~
~
~
Snooze
This Material Copyrighted by Its Respective Manufacturer
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