- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄369690 > GS84018T-100IT x18 Fast Synchronous SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | GS84018T-100IT |
| 英文描述： | x18 Fast Synchronous SRAM |
| 中文描述： | x18快速同步SRAM |
| 文件頁(yè)數(shù)： | 11/31頁(yè) |
| 文件大?。?/td> | 717K |
| 代理商： | GS84018T-100IT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)
Rev: 2.05 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
11/31
1999, Giga Semiconductor, Inc.
.
GS84018/32/36T/B-180/166/150/100
Mode Pin Functions
Note:
There are pull up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Byte Write Truth Table
Note:
1.
2.
3.
4.
All byte outputs are active in read cycles regardle
ss
of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
C
” and “
D
” are only available on the x32 and x36 versions.
Mode Name
Pin Name
State
L
H or NC
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte
A
H
L
L
H
H
H
2, 3
Write byte
B
H
L
H
L
H
H
2, 3
Write byte
C
H
L
H
H
L
H
2, 3, 4
Write byte
D
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
1st address
2nd address
3rd address
4th address
This Material Copyrighted by Its Respective Manufacturer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS84018T-150 | x18 Fast Synchronous SRAM |
| GS84018T-150I | x18 Fast Synchronous SRAM |
| GS84018T-150IT | x18 Fast Synchronous SRAM |
| GS84018T-166 | x18 Fast Synchronous SRAM |
| GS84018T-166I | x18 Fast Synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS84018T-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| GS84018T-150I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| GS84018T-150IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| GS84018T-166 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| GS84018T-166I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。