參數(shù)資料
型號(hào): GS84018B-100I
英文描述: x18 Fast Synchronous SRAM
中文描述: x18快速同步SRAM
文件頁(yè)數(shù): 14/31頁(yè)
文件大?。?/td> 717K
代理商: GS84018B-100I
Rev: 2.05 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
14/31
1999, Giga Semiconductor, Inc.
.
GS84018/32/36T/B-180/166/150/100
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
3.
This Material Copyrighted by Its Respective Manufacturer
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