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參數(shù)資料
| 型號： | GS8342S36AE-200S |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大?。?/td> | 1576K |
| 代理商： | GS8342S36AE-200S |
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Preliminary
GS8342S08/09/18/36AE-333/300/250/200/167
36Mb Burst of 2
DDR SigmaSIO-II SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 6/2006
1/37
2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaSIO Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write (x36, x18, and x9) and Nybble Write (x8) function
DLL circuitry for wide output data valid window and future
frequency scaling
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ mode pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
Pin-compatible with future 72Mb and 144Mb devices
SigmaRAM Family Overview
GS8342S08/09/18/36AE are built in compliance with the
SigmaSIO-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
JEDEC Std. MO-216, Variation CAB-1
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 2M x 18 has a 1M
addressable index).
Parameter Synopsis
- 333
-300
-250
-200
-167
tKHKH
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.5 ns
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相關代理商/技術參數(shù) |
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|---|---|
| GS8342S36AE-333 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 1MX36 0.45NS 165FPBGA - Trays |
| GS8342S36BD-400 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342S36GE-400 | 制造商:GSI Technology 功能描述:1M X 36 (36 MEG)SIGMASIO-II SEPERATE I/O BURST OF 2 - Trays |
| GS8342T06BD-450 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342T06BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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