參數(shù)資料
型號(hào)： GS8324Z36B-150IT
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 1M X 36 ZBT SRAM, 10 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, BGA-119
文件頁(yè)數(shù)： 35/46頁(yè)
文件大小： 1157K
代理商： GS8324Z36B-150IT
Rev: 1.00 10/2001
40/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Notes:
1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.
2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.
3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.
4. 1 = no connect, internally set to logic value 1
5. 0 = no connect, internally set to logic value 0
6. X = no connect, value is undefined
GS8324Z18/36/72 Boundary Scan Chain Order
Order
x72
x36
x18
Bump
x72
x36 x18
1(TBD)
相關(guān)PDF資料
PDF描述
GS8324Z36GB-250IT 1M X 36 ZBT SRAM, 6 ns, PBGA119
GS8324Z72GC-133IT 512K X 72 ZBT SRAM, 10 ns, PBGA209
GS840E18GB-100T 256K X 18 CACHE SRAM, 12 ns, PBGA119
GS840E18GB-180 256K X 18 CACHE SRAM, 8 ns, PBGA119
GS8641E18F-200IT 4M X 18 CACHE SRAM, 7.5 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8324Z36B-200I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays
GS8324Z72C200 制造商:G.S.I. 功能描述:
GS8342D06BD-350 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342D06BD-500 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342D06BD-550 制造商:GSI Technology 功能描述:165 FBGA - Bulk
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