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    參數(shù)資料
    型號(hào)： GS8322Z18E-200IV
    廠商： GSI TECHNOLOGY
    元件分類： DRAM
    英文描述： 36Mb Pipelined and Flow Through Synchronous NBT SRAM
    中文描述： 2M X 18 ZBT SRAM, 7.5 ns, PBGA165
    封裝： 15 X 17 MM, 1 MM PITCH, FPBGA-165
    文件頁(yè)數(shù)： 30/39頁(yè)
    文件大?。?/td> 973K
    代理商： GS8322Z18E-200IV
    GS8322Z18/36/72(B/E/C)-xxxV
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    Rev: 1.05 6/2006
    30/39
    2002, GSI Technology
    JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
    Parameter
    Symbol
    Min.
    Max.
    Unit Notes
    1.8 V Test Port Input Low Voltage
    V
    ILJ1
    –
    0.3
    0.3 * V
    DD1
    V
    1
    2.5 V Test Port Input Low Voltage
    V
    ILJ2
    –
    0.3
    0.3 * V
    DD2
    V
    1
    1.8 V Test Port Input High Voltage
    V
    IHJ1
    0.6 * V
    DD1
    V
    DD1
    +0.3
    V
    1
    2.5 V Test Port Input High Voltage
    V
    IHJ2
    0.6 * V
    DD2
    V
    DD2
    +0.3
    V
    1
    TMS, TCK and TDI Input Leakage Current
    I
    INHJ
    –
    300
    1
    uA
    2
    TMS, TCK and TDI Input Leakage Current
    I
    INLJ
    –
    1
    100
    uA
    3
    TDO Output Leakage Current
    I
    OLJ
    –
    1
    1
    uA
    4
    Test Port Output High Voltage
    V
    OHJ
    1.7
    —
    V
    5, 6
    Test Port Output Low Voltage
    V
    OLJ
    —
    0.4
    V
    5, 7
    Test Port Output CMOS High
    V
    OHJC
    V
    DDQ
    – 100 mV
    —
    V
    5, 8
    Test Port Output CMOS Low
    V
    OLJC
    —
    100 mV
    V
    5, 9
    Notes:
    1.
    2.
    3.
    4.
    5.
    6.
    7.
    8.
    9.
    Input Under/overshoot voltage must be
    –
    2 V < Vi < V
    DDn
    +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
    V
    ILJ
    ≤
    V
    IN
    ≤
    V
    DDn
    0 V
    ≤
    V
    IN
    ≤
    V
    ILJn
    Output Disable, V
    OUT
    = 0 to V
    DDn
    The TDO output driver is served by the V
    DDQ
    supply.
    I
    OHJ
    =
    –
    4 mA
    I
    OLJ
    = + 4 mA
    I
    OHJC
    = –100 uA
    I
    OLJC
    = +100 uA
    JTAG Port AC Test Conditions
    Notes:
    1.
    2.
    Include scope and jig capacitance.
    Test conditions as shown unless otherwise noted.
    Parameter
    Conditions
    Input high level
    V
    DD
    – 0.2 V
    Input low level
    0.2 V
    Input slew rate
    1 V/ns
    Input reference level
    V
    DDQ
    /2
    Output reference level
    V
    DDQ
    /2
    DQ
    V
    DDQ
    /2
    50
    30pF
    *
    JTAG Port AC Test Load
    * Distributed Test Jig Capacitance
    相關(guān)PDF資料
    PDF描述
    GS8322Z18E-200V 36Mb Pipelined and Flow Through Synchronous NBT SRAM
    GS8322Z18E-225V 36Mb Pipelined and Flow Through Synchronous NBT SRAM
    GS8322Z18E-250IV 36Mb Pipelined and Flow Through Synchronous NBT SRAM
    GS8322Z18E-250V 36Mb Pipelined and Flow Through Synchronous NBT SRAM
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    GS8322Z18E-200V 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 36MBIT 2MX18 7.5NS/3NS 165FPBGA - Trays
    GS8322Z18E-225 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 36MBIT 2MX18 7NS/2.7NS 165FBGA - Trays
    GS8322Z18E-225I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 36MBIT 2MX18 7NS/2.7NS 165FBGA - Trays
    GS8322Z18E-225IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 36MBIT 2MX18 7NS/3NS 165FPBGA - Trays
    GS8322Z18E-225M 制造商:GSI Technology 功能描述:165 BGA - Bulk
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