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參數(shù)資料
| 型號： | GS820V32T5 |
| 英文描述： | x32 Fast Synchronous SRAM |
| 中文描述： | X32號，快速同步SRAM |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 649K |
| 代理商： | GS820V32T5 |
Rev: 1.08 2/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
8/23
2000, Giga Semiconductor, Inc.
GS82032AT/Q-200/180/166/133/100
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data
Input Set Up Time.
3.
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| GS820V32T5I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| GS820V32T6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
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