參數(shù)資料
型號: GS82032Q-5
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 64K x 32 2M Synchronous Burst SRAM
中文描述: 64K的× 32 200萬同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 8/23頁
文件大?。?/td> 760K
代理商: GS82032Q-5
Rev: 1.04 2/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
8/23
2000, Giga Semiconductor, Inc.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
3.
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