參數(shù)資料
型號(hào): GS82032A
廠商: GSI TECHNOLOGY
英文描述: 2Mb(64K x 32Bit) Synchronous Burst SRAM(2M位(64K x 32位)同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
中文描述: 2MB的(64K的x 32位)同步突發(fā)靜態(tài)存儲(chǔ)器(200萬位(64K的× 32位)同步靜態(tài)隨機(jī)存儲(chǔ)器(帶2位脈沖地址計(jì)數(shù)器))
文件頁數(shù): 19/23頁
文件大小: 757K
代理商: GS82032A
Rev: 1.07 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
19/23
2000, Giga Semiconductor, Inc.
GS82032AT/Q-200/180/166/133/100
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
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~
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Snooze
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PDF描述
GS82032 2Mb(64K x 32Bit) Synchronous Burst SRAM(2M位(64K x 32位)同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
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GS82032AGQ-133 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays
GS82032AGQ-133I 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays
GS82032AGQ-150I 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays
GS82032AGQ-166 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays
GS82032AGQ-166I 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays