參數(shù)資料
型號(hào)： GS8180S36
廠商： GSI TECHNOLOGY
英文描述： 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述： 為512k × 36Bit分離I / O西格瑪?shù)腄DR SRAM的（為512k × 36位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM）
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 853K
代理商： GS8180S36
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
9/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
Alternating Read-Write Operations
In order to make interface with Separate I/O Sigma RAMs as straightforward as possible, the control logic has been optimized
specifically for alternate read-write cycles. A Separate I/O Sigma RAM can begin an alternating sequence of reads and writes with
either a read or a write. The status of the W pin is evaluated at the beginning of the first active cycle after the RAM has been
deselected via E1. The status of the W pin is not checked again until the RAM has been deselected and reselected via E1. The user
may introduce as few or as many deselect cycles between active cycles as are desired, but the user must inform the RAM at the
beginning of the first active cycle, via W, whether to restart with a read or write cycle.
All address, data, and control inputs (with the exception of EP2, EP3, and the mode pins, M2–M4) are synchronized to rising clock
edges. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one
of the Enable inputs will deactivate the device.
It should be noted that ONLY deactivation of the RAM via E2 and/or E3 (a
Bank Deselect) deactivates the Echo Clocks, CQ1–CQn. Conversely, only E1 is used to identify a “first active cycle” event.
Read Operations
Read operation will be initiated at the rising edge of clock if the previous cycle was a write and all three chip enables (E1, E2, and
E3) are active. If the previous cycle was a deselect (E1 high), then all three chip enables must be active and the Write enable signal
(W) must be deasserted high. The address presented to the address inputs is latched in to address register and presented to the
memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to
propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the
output register and onto the Output pins.
Write Operations
Write operation will be initiated at the rising edge of clock if the previous cycle was a read and all three chip enables (E1, E2, and
E3) are active. If the previous cycle was a deselect (E1 high), then all three chip enables must be active and the Write enable signal
(W) must be asserted low. Separate I/O Sigma RAMs employ an “Late Write” protocol, meaning the Address input and the Write
command are due into the RAM on the same rising edge of clock, but Data In is due into the RAM on the next rising edge of clock.
Separate I/O Sigma RAMs accumulate the input data in a register and then feeds the accumulated data into the array at the first
opportunity. Separate I/O Sigma RAMs are fully coherent, which is to say, if the user asks for data just written to the RAM, the
most recent copy of the data will be read directly out of the holding registers rather than from the array (which contains stale data).
相關(guān)PDF資料
PDF描述
GS8180S18 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
GS8180S09 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
GS820322T-138 64K x 32 2M Synchronous Burst SRAM
GS82032Q-100 64K x 32 2M Synchronous Burst SRAM
GS82032Q-117 64K x 32 2M Synchronous Burst SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8182D08BD-167 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays
GS8182D08BD-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays
GS8182D08BD-375 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays
GS8182D09BD-400 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 2M X 9 0.45NS 165FPBGA - Trays
GS8182D18BD-167 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.5NS 165FPBGA - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*