- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383036 > GS8180D18 (GSI TECHNOLOGY) 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) PDF資料下載
參數(shù)資料
| 型號： | GS8180D18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| 中文描述： | 1兆x 18位獨立的I / O西格瑪?shù)腄DR SRAM的（100萬× 18位獨立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM） |
| 文件頁數(shù)： | 21/33頁 |
| 文件大?。?/td> | 874K |
| 代理商： | GS8180D18 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
21/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-275
-250
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Clock Cycle Time
tKHKH
3.0
—
3.3
—
3.6
—
4.0
—
ns
—
Clock High to Output Valid
tKHQV
—
1.6
—
1.8
—
1.9
—
2.1
ns
—
Clock High to Output in High-Z
tKHQZ
0.5
1.6
0.5
1.8
0.5
1.9
0.5
2.1
ns
1
Clock High to Output Invalid
tKHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
—
Clock High to Output in Low-Z
tKHQX1
0.5
—
0.5
—
0.5
—
0.5
—
ns
1
Clock High to Echo Clock Low-Z
tKHCX1
0.5
—
0.5
—
0.5
—
0.5
—
ns
2, 4
Clock High to Echo Clock High
tKHCH
0.6
1.5
0.6
1.7
0.6
1.8
0.6
2.0
ns
4
Clock Low to Echo Clock Low
tKLCL
0.6
1.5
0.6
1.7
0.6
1.8
0.6
2.0
ns
4
Output Invalid to Echo Clock High
tCHQX
—
–0.5
—
–0.6
—
–0.6
—
–0.7
ns
2
Output Invalid to Echo Clock Low
tCLQX
—
–0.5
—
–0.6
—
–0.6
—
–0.7
ns
2
Echo Clock High to Output Valid
tCHQV
—
0.5
—
0.6
—
0.6
—
0.7
ns
2
Echo Clock Low to Output Valid
tCLQV
—
0.5
—
0.6
—
0.6
—
0.7
ns
2
Clock High to Echo Clock High-Z
tKHCZ
0.5
1.5
0.5
1.7
0.5
1.8
0.5
2.0
ns
1, 2
Clock HIGH Time
tKHKL
1.2
—
1.3
—
1.4
—
1.6
—
ns
—
Clock LOW Time
tKLKH
1.2
—
1.3
—
1.4
—
1.6
—
ns
—
Address Valid to Clock High
tAVKH
0.6
—
0.7
—
0.7
—
0.8
—
ns
—
Clock High to Address Don’t Care
tKHAX
0.4
—
0.4
—
0.5
—
0.5
—
ns
—
Enable Valid to Clock High
tEVKH
0.6
—
0.7
—
0.7
—
0.8
—
ns
—
Clock High to Enable Don’t Care
tKHEX
0.4
—
0.4
—
0.5
—
0.5
—
ns
—
Write Valid to Clock High
tWVKH
0.6
—
0.7
—
0.7
—
0.8
—
ns
—
Clock High to Write Don’t Care
tKHWX
0.4
—
0.4
—
0.5
—
0.5
—
ns
—
Data In Valid to Clock High
tDVKH
0.6
—
0.7
—
0.7
—
0.8
—
ns
—
Clock High to Data In Don’t Care
tKHDX
0.4
—
0.4
—
0.5
—
0.5
—
ns
—
Data In Valid to Clock Low
tDVKL
0.6
—
0.7
—
0.7
—
0.8
—
ns
Clock Low to Data In Don’t Care
Notes:
1.
Measured at 100 mV from steady state. Not 100% tested.
2.
Guaranteed by design. Not 100% tested.
3.
For any specific temperature and voltage tKHCZ < tKHCX1.
4.
Tested using AC Test Load B
tKLDX
0.4
—
0.4
—
0.5
—
0.5
—
ns
相關PDF資料 |
PDF描述 |
|---|---|
| GS8180S36 | 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S09 | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS820322T-138 | 64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-100 | 64K x 32 2M Synchronous Burst SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS8180Q36D-167X | 制造商:GSI Technology 功能描述:512K X 36 (18 MEG)SIGMA QUAD I -SEPERATE I/O BURST OF 2 - Trays |
| GS8180QV36BGD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 512KX36 2.5NS 165FPBGA - Trays |
| GS8180QV36BGD-167I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 512KX36 2.5NS 165FPBGA - Trays |
| GS8182D08BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays |
| GS8182D08BD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。