- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383036 > GS8170DW36AGC-250I (GSI TECHNOLOGY) 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | GS8170DW36AGC-250I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 766K |
| 代理商： | GS8170DW36AGC-250I |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
5/32
2003, GSI Technology
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Single Data Rate Pipelined Read
F
D
Address
Read
CK
E
QC
QD
CQ
Read
Deselect
Read
Read
A
XX
C
Key
Hi-Z
Access
ADV
QA
/E
1
/W
DQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8170DW36AGC-300 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36AGC-300I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36AGC-333 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170S36 | 16Mb（512K x 36Bit）Synchronous SRAM(16M位（512K x 36位）同步靜態(tài)RAM) |
| GS8170S18 | 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8170DW36AGC-300 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170DW36AGC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170DW36AGC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AGC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36C-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。