參數(shù)資料
型號: GS8170DD36C-333I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
中文描述: 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 12/29頁
文件大?。?/td> 537K
代理商: GS8170DD36C-333I
GS8170DD36C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
12/29
2002, GSI Technology, Inc.
DDR Late Write, Pipelined Read Truth Table
CK
E1
(t
n
)
E
(t
n
)
ADV
(t
n
)
W
(t
n
)
Previous
Operation
Current Operation
DQ/CQ
(t
n
)
DQ/CQ
(t
n+
)
DQ/CQ
(t
n+1
)
DQ/CQ
(t
n+1
)
0
1
X
F
0
X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
0
1
X
X
1
X
Bank Deselect
Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
0
1
1
T
0
X
X
Deselect
***/***
Hi-Z/CQ
0
1
X
X
1
X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
0
1
0
T
0
0
X
Write
Loads new address
***/***
D1/CQ
D2/CQ
0
1
X
X
1
X
Write
Write Continue
Increments address by 2
Dn-2/CQ
Dn-1/CQ
Dn/CQ
Dn+1/CQ
0
1
0
T
0
1
X
Read
Loads new address
***/***
Q1/CQ
Q2/CQ
0
1
X
X
1
X
Read
Read Continue
Increments address by 2
Qn-2/CQ
Qn-2/CQ
Qn/CQ
Qn+1/CQ
Notes:
1.
2.
3.
4.
5.
6.
If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
“1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
“***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer a total of four (4) distinct pieces of
data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
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